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ordering number : enn7441a 22004tn (ot) no. 7441-1/19 overview the STK672-060 is a stepping motor driver hybrid ic that adopts power mosfets in its output stage. it features a built-in microstepping controller that implements unipolar constant current pwm drive. since this ic includes a 4-phase distribution controller for stepping motors, it can contribute not only to system simplification but to circuit standardization as well. the STK672-060 supports the 2 phase, 1-2 phase, w1-2 phase, 2w1-2 phase, and 4w1-2 phase excitation (drive) methods and can control the motor with the basic stepping angle of the stepping motor divided into up to 16 divisions. motor rotation can also be controlled with just the clock signal. this hybrid ic can implement highly efficient drive with high motor torque, low vibration, low noise, and fast response. as compared to the earlier sanyo stk672-010 series, the STK672-060 features a smaller package, fewer required external components, and improvements to the controller for high functionality high performance microstepping drive. applications ? facsimile unit stepping motor drive for both transmission and reception ? paper feed and optical system stepping motor drive in copiers ? laser printer drum drive ? printer carriage stepping motor drive ? x/y plotter pen drive ? other stepping motor applications features ? the STK672-060 can implement a stepping motor drive system with just the provision of a dc power supply and a clock pulse generator. the excitation mode settings (m1, m2, and m3) select one of five excitation methods. ? 2 phase excitation ? 1-2 phase excitation ? w1-2 phase excitation ? 2w1-2 phase excitation ? 4w1-2 phase excitation continued on next page. package dimensions unit: mm 4161-sip22 STK672-060 sanyo electric co.,ltd. semiconductor company tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan stepping motor driver (sine wave drive) output current: 1.2 a (no heat sink * ) unipolar constant-current chopper (external excitation pwm) circuit with built- in microstepping controller thick-film hybrid ic any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircrafts control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein. 122 53.0 0.5 2.0 22.0 9.0 0.4 2.9 4.0 1.0 21 2 = 42 sanyo: sip22 [STK672-060] notes *: conditions: v cc 1 = 24 v, i oh = 1.2 a, 2w1-2 excitation mode
no. 7441- 2 /19 STK672-060 ? to match the motor characteristics, the vector locus during microstepping drive can be selected to be any one of four modes: circular mode, one inside mode, and two outside modes. ? the phase is retained if excitation is switched during operation. ? the excitation phase state can be verified in real time using the mo1, mo2, and moi signal output pins. ? the clock input counter block supports two signalsense modes selected by the high or low state of the m3 pin. rising edges only both rising and falling edges ? the clk and return input pins have built-in circuits that prevent malfunctions due to external noise pulses. ? both an enable and a reset pin are provided as schmitt trigger inputs with built-in 20 k (typical) pull- up resistors. ? no audible noise is generated by the differences in the time constant between phases a and b when the motor position is held fixed due to the adoption of external excitation. ? the reference voltage vref can be set to any level between 0 and 1/2 v cc 2. this allows the STK672-060 to provide microstepping operation even for small motor currents. ? provides a wide range of operating supply voltage required for external excitation pwm drive (v cc 1 = 10 to 45 v). ? current detection resistor (0.22 ) built-in the hybrid ic itself. ? power mosfets adopted for low drive loss. ? provides a motor output drive current of i oh = 1.2 a. continued from preceding page. parameter symbol conditions ratings unit maximum supply voltage 1 v cc 1 max no signal 52 v maximum supply voltage 2 v cc 2 max no signal C0.3 to +7.0 v input voltage v in max logic input pins C0.3 to +7.0 v phase output current i oh max 0.5 s, 1 pulse, when v cc 1 applied 1.6 a repeated avalanche resistance ear max 25 mj power dissipation pd max q c-a = 0 7 w operating ic substrate temperature tc max 105 c junction temperature tj max 150 c storage temperature tstg C40 to +125 c specifications absolute maximum ratings at tc = 25 c parameter symbol conditions ratings unit supply voltage 1 v cc 1 when the input signal is present 10 to 45 v supply voltage 2 v cc 2 when the input signal is present 5 5% v input voltage v ih 0 to v cc 2 v phase drive voltage handling capacity v dss transistors 1, 2, 3, and 4 (outputs a, a, b, and b) 100 (min) v phase current i oh max duty 50% 1.2 (max) a allowable operating ranges at ta = 25 c
no. 7441- 3 /19 STK672-060 parameter symbol conditions ratings unit min typ max control power supply current i cc the hybrid ic pin 7 input, enable = low 2.5 14 ma output saturation voltage vsat r l = 23 (i 1a) 0.8 1.1 v average output current io ave load: r = 3.5 . l = 3.8 mh per phase, vref 1.69 v 0.470 0.524 0.580 a fet diode forward voltage vdf if = 1 a 1.2 1.8 v [control input pins] input voltage v ih except for the vref pin 4 v v il except for the vref pin 1 v input current i ih except for the vref pin 0 1 10 a i il except for the vref pin 125 250 510 a [vref input pin] input voltage v i h-ic pin 8 0 2.5 v input current i i h-ic pin 8, v i = 2.5 v 330 415 545 a [control output pins] output voltage v oh i = C3 ma, moi, mo1, mo2 pins 2.4 v v ol i = +3 ma, moi, mo1, mo2 pins 0.4 v [current division ratio (a ? b)] 2w1-2, w1-2, 1-2 vref q = 1/8 100 % 2w1-2, w1-2 vref q = 2/8 92 % 2w1-2 vref q = 3/8 83 % 2w1-2, w1-2, 1-2 vref q = 4/8 71 % 2w1-2 vref q = 5/8 55 % 2w1-2, w1-2 vref q = 6/8 40 % 2w1-2 vref q = 7/8 21 % 2 vref 100 % pwm frequency fc 37 47 57 khz electrical characteristics at tc = 25 c, v cc 1 = 24 v, v cc 2 = 5 v notes: a constant voltage power supply must be used. design target values are shown for the current division ratios.
20 16 18 11 14 15 10 9 7 8 6 5 2 1 + + 4 3 m1 m2 cwb clk m3 reset 17 return mo1 19 moi 21 mo2 enable 22 sg sub pg b b a a vref m5 m4 v cc 2 itf02264 12 13 excitation mode setting rising edge/falling edge detection switching rising edge detection excitation state monitor rc oscillator refe rence clock generator phase advance counter current division ratio switching pseudo-sine wave generator phase excitation signal generator pwm control block diagram no. 7441- 4 /19 STK672-060
+ 14 9 10 8 16 22 1 5 2 6 a a b a b a b sw2 sw1 b 7 18 v cc 2 v cc 2 vref=1.69v 0v 5v 0v v cc 1 v cc 1 STK672-060 start low for i cc itf02268 a a 9 22 7 v cc 2 m1 STK672-060 itf02267 10 m2 11 m3 12 m4 13 m5 14 14 clk 15 cwb 16 reset 17 return 18 enable 8 vref i il i ih a 22 1 2 5 6 a a b b 7 STK672-060 v a itf02266 3 4 test circuit diagrams no. 7441- 5 /19 STK672-060 14 9 10 8 16 22 1 3 4 2 5 6 a 23 a b b 7 + v cc 2 v cc 2 STK672-060 vref=2.5v start v v cc 1 itf02265 vsat vdf i ih , i il ioave, icc, fc when measuring ioave: set switch sw1 to the b position, set vref = 1.69 v when measuring fc: set switch sw1 to the a position, set vref = 0 v when measuring i cc : set enable low.
no. 7441- 6 /19 STK672-060 8 6 a a 7 22 12 11 10 9 14 13 15 14 18 16 17 19 + + v cc 2=5v v cc 2=5v sg 100 f or higher pg vref ro1 ro2 v cc 2=5v simple power-on reset circuit (this circuit cannot be used to detect drops in the supply voltage.) two-phase stepping motor clk 1k enable ret v f 0.3v reset moi v cc 1=10v to 45v STK672-060 itf02269 b b rox 5 2 1 3 4 20 mo1 21 mo2 ioave i ol i oh oa motor current waveform a13262 power-on reset the application must perform a power-on reset operation when v cc 2 power is first applied to this hybrid ic. application circuit that used 2w1-2 phase excitation (microstepping operation) mode motor current setting procedure the motor current i oh is set by the voltage on pin 8, vref. the following formulas show the relationship between i oh and vref: rox = (ro2 6 k ) (ro2 + 6 k ) .................... (1) vref = v cc 2 rox (ro1 + rox) ..................... (2) 1 vref i oh = ................................................... (3) k rs k: 7.66 (voltage divider ratio), rs: 0.22 (this is the hybrid ic's internal current detection resistor. it has a tolerance of 3%.) motor currents range from the setting current (0.05 to 0.1 a) due to the frequency of the duty cycle set by the oscillator to the current given in the allowable operating ranges (i oh = 1.2 a). function table m2 0 0 1 1 m1 0 1 0 1 phase switching clk edge timing m3 1 2 phase excitation 1-2 phase excitation w1-2 phase excitation 2w1-2 phase excitation rising edge only 0 1-2 phase excitation w1-2 phase excitation 2w1-2 phase excitation 4w1-2 phase excitation both rising and falling edges forward reverse cwb 0 1 enable the motor current is cut when this pin is set to the low level. reset active low a value of about 100 is recommended for ro2 to minimize the influence of the 6 k internal resistance of the vref pin. rox: input impedance of 6 k 30% a a b b mo1 1 0 0 1 mo2 0 0 1 1
no. 7441- 7 /19 STK672-060 recommendations for pcb designs this hybrid ic has three ground pins: the pg pins (pins 3 and 4) and the sg pin (pin 22). these pins are connected internally. two power supplies are required: one power supply for motor drive and another for the hybrid ic 5 v control system. if there are problems with the ground connections for these power supplies, that can in turn cause the motor current waveform to become unstable, an increase in audible motor noise, or increased motor vibration. the ground lines must be designed appropriately. this section describes two ground connection methods. ? when the grounds for the motor drive power supply and the hybrid ic 5 v power supply are connected close to the power supplies a) if pg and sg are shorted at the power supply side, connect only the pg line to pins 3 and 4 on the hybrid ic. verify that voltage drops due to common line impedances do not occur. note that v cc 2 is required to be within 5% in the specifications. b) connecting the vref ground to pin 22 provides more stable current waveforms. c) for initial values, use 100 f or higher for c1 and 10 f or higher for c2. c1 must be located close to the hybrid ic and the capacitor ground line must be as short as possible. sg 3 4 pg STK672-060 v cc 2 vref clk 7 8 22 14 - - + - - + sg pg motor dr iv e po w er supply 5 v po w er supply cloc k gener ation oscillator c1 c2 10 f or higher + + 100 f or higher stepping motor itf02270 ? when the grounds for the motor drive power supply and the hybrid ic 5 v power supply are separated a) place the capacitor c1 (100 f or higher) as close to the hybrid ic as possible. this capacitor's ground line must be as short as possible. connect the capacitor c2 of an appropriate value if required. it's ground line must be as short as possible. sg 3 4 pg STK672-060 v cc 2 vref clk 7 8 22 14 - - + - - + sg pg c1 + + itf02271 motor dr iv e po w er supply 5 v po w er supply cloc k gener ation oscillator c2 10 f or higher 100 f or higher isolated stepping motor
no. 7441- 8 /19 STK672-060 d1 rs l2 v cc 1 i off l1 mosfet and enable divider latch circuit rc oscillator current divider noise filter ? (control signal) q s r 800khz 45khz vref a=1 + i on itf02272 a a m4 m5 ic operation external excitation chopping driver block since this hybrid ic adopts an external excitation method, no external oscillator circuit is required. if a high level is input on the ?a line in the driver block basic circuit in the figure and the mosfet is turned on, the comparator + input will go to the low level and the comparator output will go to the low level. meanwhile, since the set signal is input during the pmw period, the q output will go to the high level and the initial state of the mosfet will be the on state. the current i on that flows in the mosfet will pass through l1 generating a potential difference across rs. then, when the rs potential becomes the same as the vref potential, the comparator output will invert, the reset signal will be generated, and the q output will invert, into the low level. this turns the mosfet off and the energy stored in l1 is induced in l2, and i off is regenerated to the power supply. this state is maintained for the time that the set signal is input to the latch circuit. the q output is turned on and off repeatedly by the set and reset signals in this manner, which implements constant current control. the resistor and capacitor connected at the comparator input synchronize with the pwm period of the spike absorption circuit. because of the fixed period due to the external excitation method adopted and synchronized pwm system, this circuit can minimize hold noise generated when the motor position is locked. driver block basic circuit structure input pin description pin no. pin function pin circuit type 14 clk phase switching clock cmos schmitt trigger circuit with built-in pull-up resistor 15 cwb rotation direction setting (cw/ccw) cmos schmitt trigger circuit with built-in pull-up resistor 17 return forcible return to phase origin cmos schmitt trigger circuit with built-in pull-up resistor 18 enable output cutoff cmos schmitt trigger circuit with built-in pull-up resistor 9, 10, 11 m1, m2, m3 excitation mode setting cmos schmitt trigger circuit with built-in pull-up resistor 12, 13 m4, m5 vector locus setting cmos schmitt trigger circuit with built-in pull-up resistor 16 reset system reset cmos schmitt trigger circuit with built-in pull-up resistor 8 vref current value setting operational amplifier input
? input signal functions and timing clk (phase switching clock) input frequency range: dc to 50 khz minimum pulse width: 10 s duty: 40 to 60% (the minimum pulse width takes precedence when m3 is high) pin circuit type: cmos schmitt trigger with built-in pull-up resistor (20 k typical) a multi-stage noise filter is built in. function when m3 is high or open: the excited phase is advanced by one step on each rising edge of clk signal. when m3 is low: the phase is advanced 2 steps on the rising and falling edges of the clk signal. cwb (rotation setting procedure) pin circuit type: cmos schmitt trigger with built-in pull-up resistor (20 k typical) function when cwb is low: rotation in the clockwise direction. when cwb is high: rotation in the counterclockwise direction note: when m3 is low, the cwb input must not be changed within 6.25 s of a rising or falling edge on the clk input. return (forcible return to the origin point for the current phase) pin circuit type: cmos schmitt trigger with built-in pull-up resistor (20 k typical) built-in noise filter note: the motor is forcibly moved to the origin point for the current phase by changing the input level on this pin from low to high. when unused, this pin must normallyr be left open or connected to the v cc 2. enable (on/off control of the a, a, b, and b excitation drive outputs and selection of the internal operate or hold state of the hybrid ic itself) pin circuit type: cmos schmitt trigger with built-in pull-up resistor (20 k typical) function when enable is high or open: normal operating state when enable is low: the hybrid ic goes to the hold state, and the excitation drive output (motor current) is forcibly turned off (the output current is cut off). in this state, the hybrid ic system clock is stopped, and the hybrid ic is not affected by any changes in the state of the input pins other than the reset input. clk input acquisition timing (when m3 is low) no. 7441- 9 /19 STK672-060 a13264 clk input excitation counter up/down control output switching timing system clock phase excitation counter clock control output timing
m1, m2, and m3 (excitation mode and clk input edge timing selection) pin circuit type: cmos schmitt trigger with built-in pull-up resistor (20 k typical) timing when mode setting is enabled: do not change the mode within 5 s of a clk signal rising or falling edge. reset (resets the whole system) pin circuit type: cmos schmitt trigger with built-in pull-up resistor (20 k typical) function: the circuit states are all set to their initial values by applying a low level (with a pulse width of 10 s or longer) to the reset pin. at this time, the a and b phases are set to their origin points, regardless of the excitation mode. the output current becomes about 71% after the reset is cleared. note: the vref voltage is established by applying a reset after power is first applied. applications must perform a power-on reset operation after the v cc 2 power is applied. vref (sets the current value used as the reference for constant-current output) pin circuit type: analog input circuit function: applications can implement constant-current control of the motor excitation current at 100% of the rated current value by applying a voltage lower than the control system power supply voltage v cc 2 minus 2.5 v. this ic supports constant current control proportional to the vref voltage with an upper limit of 2.5 v. mode setting acquisition timing no. 7441- 10 /19 STK672-060 m2 0 0 1 1 m1 0 1 0 1 phase switching clk edge timing m3 1 2 phase excitation 1-2 phase excitation w1-2 phase excitation 2w1-2 phase excitation rising edge only 0 1-2 phase excitation w1-2 phase excitation 2w1-2 phase excitation 4w1-2 phase excitation both rising and falling edges m1 to m3 a13265 clk input point at which the phase excitation counter is incremented or decremented mode switching timing system clock mode setting mode switching clock hybrid ic internal setting state phase excitation clock function m4 and m5 (rotation vector locus setting for microstepping mode) m4 1 0 1 0 m5 1 0 0 1 mode circular a see the table on the following page for details on the current division ratio. 1 phase b circular phase a 2 3 itf02273
no. 7441- 11 /19 STK672-060 output pin description output signal functions and timings a, a, b, and b (motor phase excitation outputs) function: in 4 phase and 2 phase excitation modes, an interval of about 3.75 s (typical) is set up when the a and a, and b and b output signals change their state. mo1, mo2, and moi (motor phase excitation state monitoring) pin circuit type: standard cmos output function: these pins output the current phase excitation output state. pin no. pin function pin circuit type 19 moi phase excitation origin point monitor standard cmos output 20, 21 mo1, mo2 phase excitation status monitor standard cmos output phase coordinate phase a phase b phase a phase b mo1 1 0 0 1 mo2 0 1 0 1 moi outputs a 0 when the corresponding phase is at its origin, and a 1 at all other positions. mode circular a setting m3 = 0 m3 = 1 m4 = 1 m4 = 0 m4 = 1 m4 = 0 unit number of steps m5 = 1 m5 = 0 m5 = 0 m5 = 1 15 16 16 15 1/16 2w1-2 21 25 24 20 1/8 2/16 31 34 33 28 3/16 2w1-2 40 44 41 38 2/8 4/16 47 50 49 44 5/16 2w1-2 55 59 56 53 3/8 6/16 current division ratio 4w1-2 63 67 63 60 % 7/16 2w1-2 71 75 70 67 4/8 8/16 76 81 76 73 9/16 2w1-2 83 87 84 81 5/8 10/16 87 92 88 84 11/16 2w1-2 92 95 95 91 6/8 12/16 96 98 98 93 13/16 2w1-2 100 100 100 100 7/8 14/16 current division ratios as set by m3, m4, and m5 . . . . . . . . . . . . . . . . . . . . . values provided for reference purposes load conditions: v cc 1 = 24 v, v cc 2 = 5 v, r/l = 3.5 /3.8 mh
phase states at excitation switching excitation phases before and after switching excitation modes no. 7441- 12 /19 STK672-060 b 24 24 27 28 31 3 4 5 8 11 12 15 16 19 20 25 a a a 0 16 17 1 a a b b b 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 24 26 28 30 0 2 4 6 8 10 12 14 16 18 20 22 22 23 a a b b 8 9 12 4 28 20 20 24 28 0 4 8 12 16 b 24 26 28 30 a a a 0 16 18 20 22 24 28 0 4 8 12 16 20 20 28 4 12 20 28 4 0 12 16 16 18 20 22 24 25 27 29 31 1 3 5 7 9 23 22 8 24 20 10 26 18 12 16 14 28 30 6 4 2 0 11 21 13 19 15 17 24 28 0 4 8 12 16 20 26 28 30 0 2 4 6 8 10 12 14 2 4 6 b b a b a b 30 2 26 6 10 14 22 18 a b a b a b a b b a a b b 8 10 12 14 12 4 28 20 24 0 8 16 20 22 30 28 4 12 20 14 6 28 4 12 a b a b 29 1 25 5 9 13 21 24 28 0 4 8 12 16 20 17 a b a b 29 5 13 21 28 20 4 12 17 a b a b a13266 2w1-2 phase ? 2 phase w1-2 phase ? 2 phase 1-2 phase ? 2 phase 2 phase ? 1-2 phase excitation phase developed by the first clk internal pulse after the change in t he excitation mode setting with m1 and m2 excitation phase immediately prior to the excitation mode setting 2w1-2 phase ? 1-2 phase w1-2 phase ? 1-2 phase 1-2 phase ? w1-2 phase 2 phase ? w1-2 phase 2 phase ? 2w1-2 phase 2w1-2 phase ? w1-2 phase w1-2 phase ? 2w1-2 phase 1-2 phase ? 2w1-2 phase
no. 7441- 13 /19 STK672-060 excitation phases before and after switching excitation modes b 24 23 24 25 28 29 0 1 4 5 8 9 12 13 16 17 20 21 a a a 0 16 15 31 a a b b b 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 24 26 28 30 0 2 4 6 8 10 12 14 16 18 20 22 22 23 a a b b 8 7 12 4 28 20 20 24 28 0 4 8 12 16 b 24 30 a a a 0 16 22 24 28 0 4 8 12 16 20 20 28 4 12 16 28 24 20 0 4 12 16 18 20 22 24 25 27 29 31 1 3 5 7 9 23 22 8 24 20 10 26 18 12 16 14 28 30 6 4 2 0 11 21 13 19 15 17 24 28 0 4 8 12 16 20 26 28 30 0 2 4 6 8 10 12 14 6 b b a b a b 30 2 26 6 10 14 22 18 a b a b a b a b b a a b b 8 14 12 4 28 20 24 0 8 16 20 26 2 10 28 4 12 20 28 4 12 20 18 28 4 12 a b a b 30 3 27 7 11 15 23 24 28 0 4 8 12 16 20 19 a b a b 27 3 11 19 a b a b a13267 2w1-2 phase ? 2 phase w1-2 phase ? 2 phase 1-2 phase ? 2 phase 2 phase ? 1-2 phase 2w1-2 phase ? 1-2 phase w1-2 phase ? 1-2 phase 1-2 phase ? w1-2 phase 2 phase ? w1-2 phase 2 phase ? 2w1-2 phase 2w1-2 phase ? w1-2 phase w1-2 phase ? 2w1-2 phase 1-2 phase ? 2w1-2 phase
no. 7441- 14 /19 STK672-060 m1 0 m2 0 m3 reset cwb clk moi mo1 mo2 0 1 m1 1 0 1 0 m2 0 m3 reset cwb clk moi mo2 mo1 m1 1 1 0 m2 0 m3 reset cwb clk moi 0 m1 1 0 1 0 1 0 m2 m3 reset cwb clk moi mosfet gate signal comparator reterence voltage a a b b vref a vref b 100% 71% 100% 71% comparator reterence voltage vref a 100% 92% 71% 40% vref b 100% 92% 71% 40% moi mo2 mo1 comparator reterence voltage vref a 100% 92% 83% 71% 55% 40% 20% moi mo2 mo1 mosfet gate signal a a b b mosfet gate signal comparator reterence voltage a a b b vref a vref b 100% 71% 100% 71% mosfet gate signal a a b b vref b 100% 92% 83% 71% 55% 40% 20% itf02274 2 phase excitation timing chart (m3 = 1) 1-2 phase excitation timing chart (m3 = 1) w1-2 phase excitation timing chart (m3 = 1) 2w1-2 phase excitation timing chart (m3 = 1) excitation time and timing charts clk rising edge operation
clk rising and falling edge operation no. 7441- 15 /19 STK672-060 m1 0 m2 0 m3 reset cwb clk mosfet gate signal comparator reterence voltage a a b b moi mo1 mo2 vref a vref b 100% 71% 100% 71% comparator reterence voltage vref a vref b 100% 92% 83% 71% 55% 40% 20% 20% 0 m1 1 0 m2 0 m3 reset cwb clk 0 m1 0 m2 0 1 m3 reset cwb clk moi mo2 mo1 100% 92% 83% 71% 55% 40% comparator reterence voltage vref a 100% 96% 87% 76% 63% 47% 31% 63% 47% 31% 15% 92% 83% 71% 55% 40% 21% 0 m1 1 0 1 0 m2 0 m3 reset cwb clk moi mo2 mo1 0 mosfet gate signal a a b b mosfet gate signal comparator reterence voltage a a b b moi mo2 mo1 vref a vref b 100% 71% 40% 92% 100% 92% 71% 40% mosfet gate signal a a b b vref b 100% 97% 88% 77% 15% 92% 83% 71% 55% 40% 21% itf02275 1-2 phase excitation timing chart (m3 = 0) w1-2 phase excitation timing chart (m3 = 0) 2w1-2 phase excitation timing chart (m3 = 0) 4w1-2 phase excitation timing chart (m3 = 0)
thermal design the devices with the largest average power dissipation levels in this hybrid ic are the current control devices, the regenerative current diodes, and the current detection resistor. since sine wave drive is used, the average power dissipation associated with microstepping drive can be approximated by applying a waveform ratio (0.64 in this case) to square wave power dissipation in 2-phase excitation. the power dissipation levels for the available excitation modes are listed below. fclock i oh fclock 2 phase excitation pd 2ex = (vsat + vdf) i oh t2 + (vsat t1 + vdf t3) 2 2 fclock i oh fclock 1-2 phase excitation pd 1-2ex = 0.64 {(vsat + vdf) i oh t2 + (vsat t1 + vdf t3)} 4 4 fclock i oh fclock w1-2 phase excitation pd w1-2ex = 0.64 {(vsat + vdf) i oh t2 + (vsat t1 + vdf t3)} 8 8 fclock i oh fclock 2w1-2 phase excitation pd 2w1-2ex = 0.64 {(vsat + vdf) i oh t2 + (vsat t1 + vdf t3)} 16 16 fclock i oh fclock 4w1-2 phase excitation pd 4w1-2ex = 0.64 {(vsat + vdf) i oh t2 + (vsat t1 + vdf t3)} 16 16 the values of t1 and t3 can be derived from the same formula for each excitation mode Cl r + 0.7 Cl v cc 1 + 0.7 t1 = n (1 C i oh ) t3 = n () r + 0.7 v cc 1 r i oh r + v cc 1 + 0.7 the formula for t2 differs for the excitation modes. 2 3 2 phase excitation t2 = C (t1 +t3) 1-2 phase excitation t2 = C t1 fclock fclock 7 15 w1-2 phase excitation t2 = C t1 2w1-2 phase excitation t2 = C t1 fclock 4w1-2 phase excitation fclock motor phase current model (2 phase excitation) fclock: the clk pin input frequency (hz) vsat: the voltage drop (v) across the power mosfet and the current detection resistor vdf: the voltage drop (v) across the diode and the current detection resistor i oh : phase current peak-to-peak value t1: phase current rise time (s) t2: constant-current operating time (s) t3: phase switchover current regeneration time (s) v cc 1: supply voltage applied to the motor (v) l: motor inductance (h) r: motor winding resistance ( ) no. 7441- 16 /19 STK672-060 t3 t1 t2 i oh a13270
first, we determine the heat sink thermal resistance q c-a from the average power dissipation determined in the previous section. tc max: hybrid ic substrate temperature ( c) ta: end product internal temperature ( c) pd ex : hybrid ic internal average power dissipation (w) after determining q c-a from the above formula, determine the size s (cm 2 ) of the heat sink from the following graphs. the ambient temperature depends strongly on the ventilation conditions within the end product. thus the size of the heat sink must be checked carefully with the ic installed in the end product so that the back surface (the aluminum surface) of this hybrid ic never exceeds tcmax (105 c) under all possible operating conditions. next, with the hybrid ic used without fins, we determine the allowable hybrid ic average internal power dissipation from h-ic substrate thermal resistance q c-a = 23 c/w. 105 C 50 assuming that tcmax is 105 c at an ambient temperature of 50 c: pd ex = = 2.3 w 23 105 C 40 with an ambient temperature of 40 c and a tcmax of 105 c: pd ex = = 2.8 w 23 this device can be used under all operating conditions without fins provided that all dissipation values are not exceeded. (see the ? tc - pd curve.) here we determine the junction temperature tj for each device from the power dissipation for each transistor, pds and q j-c. tj = tc + q j-c pds ( c) here, to determine pds, we calculate pd ex separately for each excitation mode and determine the power dissipation pds for each device. pds = pd/4 since the power dissipation in the current detection resistor is included in the average power dissipation, here we consider that voltage drop to determine the power dissipation. vsat = i oh ron + i oh rs vdf = vdf + i oh rs the steady-state thermal resistance of the power mosfet is 18 c/w. tc max C ta q c-a = [ c/w] pd ex no. 7441- 17 /19 STK672-060 4 0 8 12 16 20 0 2 4 6 8 10 12 14 16 2 1.0 3 7 5 10 2 10 2 3 5 7 100 2 3 5 no. fin 23.0( c/w) no. fin 23.0( c/w) 40 c 50 c 60 c q c-a= tc max ta ( c/w) tc max=105 c pd itf02276 itf02277 guaranteed ambient temperature heat sink thermal resistance, q c-a c/w heat sink thermal resistance, q c-a c/w 2 mm thick al plate (without any surface finish) (with the surface painted black) ic internal average power dissipation, pd w heat sink surface area, s cm 2 vertical standing device with natural convection cooling q c-a pd q c-a s
no. 7441- 18 /19 STK672-060 50 100 200 300 150 250 350 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 0 20 40 60 80 100 10 30 50 70 90 110 10 15 20 25 30 35 40 45 0.2 0.4 0.8 1.2 0.6 1.0 0 0.2 0.4 0.8 1.2 0.6 1.0 0.1 0.3 0.7 1.1 0.5 0.9 0 0.4 0.8 1.2 0.6 1.0 1.4 0.2 0 0.4 1.2 2.0 0.8 1.6 0.2 1.0 1.8 0.6 1.4 0 0.2 0.4 0.6 0.8 1.6 1.0 1.2 1.4 0 0.4 0.8 1.2 1.6 2.0 0.2 0.6 1.0 1.4 1.8 30 35 60 40 45 50 55 0 20 40 60 80 100 140 120 4.0 4.4 4.8 5.2 5.6 6.0 4.2 4.6 5.0 5.4 5.8 vsat - - i oh vdf - - i oh itf02280 itf02281 fc - - v cc 2 fc - - tc itf02278 itf02279 30 35 60 40 45 50 55 i oh - - v cc 1 i oh - - tc itf02282 itf02283 tc=105 c vref=0v vref=0v motor current=0.5a motor current=1.0a motor current=0.5a motor current=1.0a 25 c tc=25 c 105 c 0 20 40 60 80 100 120 50 100 200 300 400 500 450 150 250 350 0 ivref - - vref ivref - - tc itf02284 itf02285 pwm frequency , fc khz pwm frequency , fc khz supply voltage , v cc 2 v substrate temperature , tc c motor current , i oh a motor current , i oh a output saturation voltage , vsat v internal diode forward voltage , vdf v motor supply voltage , v cc 1 v motor current , i oh a substrate temperature , tc c motor current , i oh a motor current=0.5a motor current=1.0a reference voltage , vref v reference voltage input current , ivref a substrate temperature , tc c reference voltage input current , ivref a
ps no. 7441- 19 /19 STK672-060 this catalog provides information as of february, 2004. specifications and information herein are subject to change without notice. specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customers products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customers products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the delivery specification for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. 5 10 20 30 40 15 25 35 0 1 2 3 4 5 10 20 40 60 30 50 70 80 90 0.5 2.0 2.5 3.0 1.0 1.5 10k 1k 2 3 5 7 100 2 3 5 7 100k 2 3 5 7 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 0 vref - - i oh ? tc - - pd(typ) itf02286 itf02288 v cc 1: 24v dc, v cc 2: 5v dc test motor: pk244-01b r: 3.5 , l: 3.3mh no heat sink, motor current = 1a 0 ? tc - - pps itf02287 2ex 2w1-2ex motor current, i oh ?a power dissipation, pd ?w clk frequency, pps ?hz reference voltage , vref ? v substrate temperature rise, ? tc ? c substrate temperature rise, ? tc ? c

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